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    Université de Neuchâtel

    Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language

    Romanowicz, Bart ; Laudon, Matthew ; Lerch, Philippe ; Renaud, Philippe ; Amann, Hans-Peter ; Boegli, Alexis ; Moser, Vincent ; Pellandini, Fausto

    In: IEEE Proceedings of European Design and Test Conference (ED&TC), 1997, p. 119-123

    The analytical modeling and simulation of conservative electrostatic, electromagnetic and electrodynamic transducers found in microsystems using a non-linear lumped-parameter approach is presented in this paper. A comparison is made between this approach and the linearized equivalent circuit method. All models of transducers are written in HDL-ATM, a proprietary analogue hardware description...

    Université de Neuchâtel

    A graphical approach to analogue behavioural modelling

    Moser, Vincent ; Nussbaum, Pascal ; Amann, Hans-Peter ; Astier, Luc ; Pellandini, Fausto

    In: IEEE Proceedings of the European Design and Test Conference (EDTC) ; European Conference on Design Automation (EDAC) ; European Test Conference (ETC) ; European Event in ASIC Design (EUROASIC), 1994, p. 535-539

    In order to master the growing complexity of analogue electronic systems, modelling and simulation of analogue hardware at various levels is absolutely necessary. This paper presents an original modelling method based on the graphical description of analogue electronic functional blocks. This method is intended to be automated and integrated into a design framework: specialists create behavioural...

    Université de Neuchâtel

    High-level modeling using extended timing diagrams - A formalism for the behavioral specification of digital hardware

    Moeschler, Philippe ; Amann, Hans-Peter ; Pellandini, Fausto

    In: IEEE Proceedings of the European Design Automation Conference (EURO-DAC), with EURO-VHDL '93, 1993, p. 494-499

    The principles of high level modeling of digital hardware circuits using the extended timing diagrams (ETD) formalism, which adds conditions, events, action expressions, and particular constraints to traditional timing diagrams, are described. Hierarchy and concurrency are also integrated so that a full top-down design becomes possible, enhancing at the same time the readability. While, for...