In: IEEE Proceedings of the European Design Automation Conference (EURO-DAC), with EURO-VHDL '93, 1993, p. 494-499
The principles of high level modeling of digital hardware circuits using the extended timing diagrams (ETD) formalism, which adds conditions, events, action expressions, and particular constraints to traditional timing diagrams, are described. Hierarchy and concurrency are also integrated so that a full top-down design becomes possible, enhancing at the same time the readability. While, for...
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