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Université de Neuchâtel

Rem, Frank J. - Power Estimation Techniques for the Purpose IEEE ProRISK 1997.pdf

Rem, Frank J. ; Gerez, Sabih H. ; Smit, Jaap ; Heubi, Alexandre ; Ansorge, Michael ; Pellandini, Fausto

In: IEEE ProRISC Workshop on Circuits, Systems and Signal Processing, 1997, p. 415-422

Architectural synthesis for digital signal processing (DSP) is the automatic generation of a VLSI implementation of a DSP algorithm. In this process, it is desirable to estimate the power consumption of potential solutions. The estimation should be fast and accurate. The dual-bit-type estimation method known from literature was taken as a basis and adapted for the goals of this research....

Université de Neuchâtel

Micro Power 14-bit A/D Converter : 45 uW At± 1.25 V and 16 K samples/s

Grisoni, L. ; Heubi, Alexandre ; Balsiger, Peter ; Pellandini, Fausto

In: 7th International Symposium on IC Technology, Systems & Applications (ISIC-97), 1997, vol. 7, no. B1, p. 39-42

Micro power converters are required for power sensitive, battery-operated devices. Keeping thisgoal in mind IMT first developed a RSD cyclic converter featuring 13 bits of dynamic range and 60 dB ofSNR. The relative precision behavior is due to technology limitations (capacitor mismatch, finite DC gain ofOTA). However, digital correction is possible and this paper presents the implementation in a...

Université de Neuchâtel

An Automated Design Methodology for the Mapping of DSP Algorithms into Low Power VLSI Architectures

Heubi, Alexandre ; Balsiger, Peter ; Pellandini, Fausto

In: 7th International Symposium on IC Technology, Systems & Applications (ISIC-97), 1997, vol. 7, no. C6, p. 649-652

A design methodology suitable for an effective low power VLSI implementation of a large class of digital signal processing algorithms is presented, which shows to be particularly well-adapted to fulfil the requirements of portable and autonomous microsystems. Starting with the precise specifications of the application algorithms, an appropriate scheduling method is first applied to optimize the...

Université de Neuchâtel

The evolution of the Urgonian platform in the Western Swiss Jura realm and its interactions with palaeoclimatic and palaeoceanographic change along the Northern Tethyan Margin (Hauterivian – earliest Aptian)

Godet, Alexis ; Föllmi, Karl (Dir.)

Thèse de doctorat : Université de Neuchâtel, 2006 ; 1904.

During more than twenty years, a controversy appeared about the age of the Urgonian formation (lower Urgonien Jaune and upper Urgonien Blanc) from the Western Swiss Jura. Depending on previous works, these formations are considered to be Late Hauterivian or Late Barremian in age. This divergence mainly results from different calibration of orbitolinids distribution, as well as divergent sequence...

Université de Neuchâtel

Microcrystalline silicon solar cells : theory, diagnosis and stability

Sculati-Meillaud, Fanny ; Shah, Arvind (Dir.)

Thèse de doctorat : Université de Neuchâtel, 2006 ; 1903.

Cette thèse traite des cellules solaires en silicium microcristallin déposées par la technique du dépôt chimique en phase vapeur assisté par plasma à très haute fréquence (Very High Frequency Plasma Enhanced Chemical Vapor Deposition, VHF PE-CVD). Le silicium microcristallin est un matériau composé d’une phase amorphe et de nanocristaux: différentes microstructures existent selon...

Université de Neuchâtel

Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language

Romanowicz, Bart ; Laudon, Matthew ; Lerch, Philippe ; Renaud, Philippe ; Amann, Hans-Peter ; Boegli, Alexis ; Moser, Vincent ; Pellandini, Fausto

In: IEEE Proceedings of European Design and Test Conference (ED&TC), 1997, p. 119-123

The analytical modeling and simulation of conservative electrostatic, electromagnetic and electrodynamic transducers found in microsystems using a non-linear lumped-parameter approach is presented in this paper. A comparison is made between this approach and the linearized equivalent circuit method. All models of transducers are written in HDL-ATM, a proprietary analogue hardware description...

Université de Neuchâtel

Generating VHDL-A-like Models Using ABSynth

Moser, Vincent ; Nussbaum, Pascal ; Amann, Hans-Peter ; Astier, Luc ; Pellandini, Fausto

In: IEEE Proceedings of European Design Automation Conference (EURO-DAC) with EURO-VHDL, 1995, p. 522-527

A method for the graphical specification and the automatic generation of analogue behavioural models is presented. This method has been implemented as a new software tool called ABSynth. The behaviour of the component to model is described as a functional diagram, which is then automatically translated into a VHDL-A-like analogue hardware description language. No syntax knowledge is necessary and...

Université de Neuchâtel

A graphical approach to analogue behavioural modelling

Moser, Vincent ; Nussbaum, Pascal ; Amann, Hans-Peter ; Astier, Luc ; Pellandini, Fausto

In: IEEE Proceedings of the European Design and Test Conference (EDTC) ; European Conference on Design Automation (EDAC) ; European Test Conference (ETC) ; European Event in ASIC Design (EUROASIC), 1994, p. 535-539

In order to master the growing complexity of analogue electronic systems, modelling and simulation of analogue hardware at various levels is absolutely necessary. This paper presents an original modelling method based on the graphical description of analogue electronic functional blocks. This method is intended to be automated and integrated into a design framework: specialists create behavioural...

Université de Neuchâtel

High-level modeling using extended timing diagrams - A formalism for the behavioral specification of digital hardware

Moeschler, Philippe ; Amann, Hans-Peter ; Pellandini, Fausto

In: IEEE Proceedings of the European Design Automation Conference (EURO-DAC), with EURO-VHDL '93, 1993, p. 494-499

The principles of high level modeling of digital hardware circuits using the extended timing diagrams (ETD) formalism, which adds conditions, events, action expressions, and particular constraints to traditional timing diagrams, are described. Hierarchy and concurrency are also integrated so that a full top-down design becomes possible, enhancing at the same time the readability. While, for...