In: Proceedings of the International Conference on Signal Processing, Applications and Technology (ICSPAT), 2000, p. 1-5
A macro-programmable DSP architecture is presented, which is very well situated for the implementation of algorithms with regular data flow graphs, like FFTs. A smart grouping of the algorithm together with the macrocode concept reduce drastically the control and address generation overhead of the DSP and shorten the computation time. This is finally manifested in very low-power consumption,...
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In: Proceedings of the International Conference on Signal Processing, Applications and Technology (ICSPAT), 2000, p. 1-5
This paper presents a high level DSP architecture compiler for cycle-constrained filters and datapath applications. The tool offers an easy way to get, from an equation representation of a filter, a synthetisable VHLD description of an application specific DSP architecture. Inputs of the DSP compiler are an equation file to define the filter structure and a resource definition file to specify the...
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In: Proceedings of the International Conference on Signal Processing, Applications and Technology (ICSPAT), 1999, p. 1-5
Micro power converters are required for power sensitive, battery-operated devices. Keeping this goal in mind IMTdeveloped a 13-bit RSD cyclic converter. However, inaccuracies (capacitor mis-match, operation amplifier...) resulted in a relative precision behaviour. The implementation of a correction algorithm in a 2μm CMOS technology is presented. It requires 1 mm2 and simulations show...
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In: Proceedings of the International Conference on Signal Processing, Applications and Technology (ICSPAT), 1996, p. 1-5
Micro power converters are required for power sensitive, battery-operated devices. Keeping this goal in mind IMTdeveloped a 13-bit RSD cyclic converter. However, inaccuracies (capacitor mis-match, operation amplifier...) resulted in a relative precision behaviour. The implementation of a correction algorithm in a 2μm CMOS technology is presented. It requires 1 mm2 and simulations show...
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In: Proceedings of the International Conference on Signal Processing, Applications and Technology (ICSPAT), 1995, p. 420-424
State of the art A/D converters are still critical in power-sensitive, battery-operated equipment like hearing aids. In this article, a new approach is presented that features excellent signal quality, 85 dB dynamic range equivalent to a 15-bit output word, 16 kHz sampling rate, 25 μW power consumption, and 0.54 mm2 chip area. Compared to standard components, the enormous power...
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In: Proceedings of the Symposium on Signal and Image Processing (GRETSI), 1995, vol. 15, p. 1065-1068
Cet article présente un exemple d'implémentation matérielle complète d'un filtre numérique en treillis RIF-RII. Des outils CAO ont été utilisés avec des modèles VHDL synthétisables optimisés pour des applications basse consommation du traitement numérique du signal. Sur la base de cette exemple, des comparaisons ont été effectuées entre la conception manuelle et une approche CAO...
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In: IEEE Signal Processing Society (DSP Deutschland), 2000, p. 1-7
Dieser Artikel präsentiert ein high-level DSP-Synthesetool für Zyklus-limitierte Filter- und Datenpfadapplikationen. Das Synthesetool bildet einen einfachen und schnellen Designweg von der Gleichungsbeschreibung eines DSP-Algorithmus bis hin zu einer synthetisierbaren VHDL-Beschreibung. Es erzeugt anwendungs-spezifische DSP-Architekturen, welche den hohen Randbedingungen von...
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In: IEEE ProRISC Workshop on Circuits, Systems and Signal Processing, 1997, p. 415-422
Architectural synthesis for digital signal processing (DSP) is the automatic generation of a VLSI implementation of a DSP algorithm. In this process, it is desirable to estimate the power consumption of potential solutions. The estimation should be fast and accurate. The dual-bit-type estimation method known from literature was taken as a basis and adapted for the goals of this research....
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In: 7th International Symposium on IC Technology, Systems & Applications (ISIC-97), 1997, vol. 7, no. B1, p. 39-42
Micro power converters are required for power sensitive, battery-operated devices. Keeping thisgoal in mind IMT first developed a RSD cyclic converter featuring 13 bits of dynamic range and 60 dB ofSNR. The relative precision behavior is due to technology limitations (capacitor mismatch, finite DC gain ofOTA). However, digital correction is possible and this paper presents the implementation in a...
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In: 7th International Symposium on IC Technology, Systems & Applications (ISIC-97), 1997, vol. 7, no. C6, p. 649-652
A design methodology suitable for an effective low power VLSI implementation of a large class of digital signal processing algorithms is presented, which shows to be particularly well-adapted to fulfil the requirements of portable and autonomous microsystems. Starting with the precise specifications of the application algorithms, an appropriate scheduling method is first applied to optimize the...
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