Département d'informatique (Laboratoire de systèmes logiques LSL)

Spyder : a reconfigurable processor development system

Iseli, Christian ; Sanchez, Eduardo (Dir.)

Thèse Ecole polytechnique fédérale de Lausanne EPFL : 1996 ; no 1476.

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    The Spyder project consists of the development of a reconfigurable processor as well as its application development environment. The name Spyder is an anagram of the first letters of "REconfigurable Processor Development SYstem", where the term reconfigurable means that the hardware of the processor can be specifically tailored for each application. Augmenting the performance of a processor implies either increasing its clock frequency or modifying its architecture. In the latter case, the solution usually adopted is to endow the processor with multiple execution units working in parallel (superscalar processors). The main problem with this kind of processors is to locate, in the sequential list of instructions of a program, batches of instructions susceptible of being executed in parallel by the different execution units of the processor. Thanks to the advent of field-programmable gate array (FPGA) circuits, new kind of superscalar processor architectures can be considered. In particular, the Spyder processor features multiple reconfigurable execution units, which can be redesigned to fit each application, a feature which greatly increases the opportunities to perform parallel computations, particularly when working with small data elements (e.g., 16 Boolean data can be packed into a single 16-bit data word and processed in parallel by a specifically designed operation in the execution unit). All the resources of the Spyder processor operate in parallel and are controlled by a very large instruction word (VLIW) 128 bits wide. The VLIW architecture allows the use of the full parallelism available to superscalar processors without requiring the complex dispatch unit needed by such processors to handle sequential scalar instructions. The goal of the Spyder project is to design and implement a superscalar processor with multiple reconfigurable execution units, as well as the software development tools (i.e., C++ compilers and a VLIW assembler) necessary to generate applications for this processor. A prototype of the Spyder processor has been implemented on a VME board, which has been installed in a VME rack along with a SPARC board acting as host computer. A C++ compiler generating netlist files for the ViewLogic CAD tools has been developed and has generated a lot of interest in the scientific community. It is now available by anonymous ftp on the Internet. Image processing applications and cellular automata simulations have been programmed on the Spyder processor. The Spyder prototype has demonstrated its ability to achieve a high level of performance with these applications.