Faculté des sciences

Generating VHDL-A-like Models Using ABSynth

Moser, Vincent ; Nussbaum, Pascal ; Amann, Hans-Peter ; Astier, Luc ; Pellandini, Fausto

In: IEEE Proceedings of European Design Automation Conference (EURO-DAC) with EURO-VHDL, 1995, p. 522-527

A method for the graphical specification and the automatic generation of analogue behavioural models is presented. This method has been implemented as a new software tool called ABSynth. The behaviour of the component to model is described as a functional diagram, which is then automatically translated into a VHDL-A-like analogue hardware description language. No syntax knowledge is necessary and... Plus

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    Summary
    A method for the graphical specification and the automatic generation of analogue behavioural models is presented. This method has been implemented as a new software tool called ABSynth. The behaviour of the component to model is described as a functional diagram, which is then automatically translated into a VHDL-A-like analogue hardware description language. No syntax knowledge is necessary and the modelling time is reduced.