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On the Mapping of Incremental Redundancy into a Physical Layer ASIC

Weber, Benjamin ; Kröll, Harald ; Benkeser, Christian ; Huang, Qiuting

In: Journal of Signal Processing Systems, 2015, vol. 78, no. 3, p. 299-312

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    Titel
    • On the Mapping of Incremental Redundancy into a Physical Layer ASIC
    Autor
    • Weber, Benjamin. ETH Zurich, Integrated Systems Laboratory, Gloriastrasse 35, 8003, Zurich, Switzerland
    • Kröll, Harald. ETH Zurich, Integrated Systems Laboratory, Gloriastrasse 35, 8003, Zurich, Switzerland
    • Benkeser, Christian. ETH Zurich, Integrated Systems Laboratory, Gloriastrasse 35, 8003, Zurich, Switzerland
    • Huang, Qiuting. ETH Zurich, Integrated Systems Laboratory, Gloriastrasse 35, 8003, Zurich, Switzerland
    Dokumententyp
    • Postprint
    Sprache
    • Englisch
    Veröffentlicht in
    • Journal of Signal Processing Systems, 2015, vol. 78, no. 3, p. 299-312. Springer US; http://www.springer-ny.com
    Andere elektronische Ausgabe
    OAI-PMH-ID
    • oai:doc.rero.ch:332886
    Summary
    Incremental Redundancy (IR) was introduced in GSM/EDGE and later adopted in Evolved EDGE in order to keep the throughput at an acceptable level. Legacy 2G networks with their ubiquitous coverage are apt to provide a fallback solution for the latest LTE networks. On the other hand, they provide a reliable data link for emerging M2M or IoT applications. IR data processing and controlling is specified in several layers of the GSM/EDGE protocol stack. In many state-of-the-art designs this leads to decentralized data processing, and thus to costly data movements between memories and hardware accelerators. This is prohibitive for emerging M2M designs, which demand lowest possible hardware resources. In this work, IR is implemented as part of a dedicated hardware baseband signal processing unit in order to unburden higher layer processing units from IR, reduce area, power consumption, and costs. The open source baseband framework MatPHY is extended for packet switched operation to facilitate the development of efficient IR hardware architectures. With the design parameters obtained from performance evaluations computed with MatPHY an IR architecture in a 130 nm CMOS technology is presented. Said architecture proves the suitability of an ASIC IR unit instead of a software solution distributed over various layers and components.