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A low-power transmission-gate-based 16-bit multiplier for digital hearing aids

Carbognani, Flavio ; Buergin, Felix ; Felber, Norbert ; Kaeslin, Hubert ; Fichtner, Wolfgang

In: Analog Integrated Circuits and Signal Processing, 2008, vol. 56, no. 1-2, p. 5-12

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    Titre
    • A low-power transmission-gate-based 16-bit multiplier for digital hearing aids
    Auteur
    • Carbognani, Flavio. D-ITET, Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, 8092, Zurich, Switzerland
    • Buergin, Felix. D-ITET, Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, 8092, Zurich, Switzerland
    • Felber, Norbert. D-ITET, Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, 8092, Zurich, Switzerland
    • Kaeslin, Hubert. D-ITET, Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, 8092, Zurich, Switzerland
    • Fichtner, Wolfgang. D-ITET, Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, 8092, Zurich, Switzerland
    Type de document
    • Postprint
    Langue
    • Anglais
    Publié dans
    • Analog Integrated Circuits and Signal Processing, 2008, vol. 56, no. 1-2, p. 5-12. Springer US; http://www.springer-ny.com
    Autre version électronique
    Identifiant OAI-PMH
    • oai:doc.rero.ch:321685
    Summary
    The most widespread 16-bit multiplier architectures are compared in terms of area occupation, dissipated energy, and EDP (Energy-Delay Product) in view of low-power low-voltage signal processing for digital hearing aids and similar applications. Transistor-level simulations including back-annotated wire parasitics confirm that the propagation of glitches along uneven and re-convergent paths results in large unproductive node activity. Because of their shorter full-adder chains, Wallace-tree multipliers indeed dissipate less energy than the carry-save (CSM) and other traditional array multipliers (6.0µW/MHz versus 10.9µW/MHz and more for 0.25µm CMOS technology at 0.75V). By combining the Wallace-tree architecture with transmission gates (TGs), a new approach is proposed to improve the energy efficiency further (3.1µW/MHz), beyond recently published low-power architectures. Besides the reduction of the overall capacitance, minimum-sized transmission gate full-adders act as RC-low-pass filters that attenuate undesired switching. Finally, minimum size TGs increase the V dd to ground resistance, hence decreasing leakage dissipation (0.55nW versus 0.84nW in CSM and 0.94nW in Wallace)