Faculté des sciences

A/D converters architectures based on cascaded incremental and cyclic structures

Rossi, Luca ; Farine, Pierre-André (Dir.) ; Tanner, Steve (Codir.) ; Nys, Olivier (Codir.) ; Willemin, Michel (Codir.)

Thèse de doctorat : Université de Neuchâtel, 2009.

Characteristics of converters are extremely wide from Gigasamples to a few samples per second for bandwidth and resolution variation from a few bits to more than 20 bits. In the field of high resolution, converters architecture are mostly based on oversampling converters. Delta-sigma converter is a common implementation of this architecture. However, in certain applications, this converter is not... More

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    Summary
    Characteristics of converters are extremely wide from Gigasamples to a few samples per second for bandwidth and resolution variation from a few bits to more than 20 bits. In the field of high resolution, converters architecture are mostly based on oversampling converters. Delta-sigma converter is a common implementation of this architecture. However, in certain applications, this converter is not very-well suited. In instrumentation and measurements, the continuously operation, the large offset and inaccurate gain of the Δ − Σ does not satisfy the specifications. The incremental converter, who is also based on Δ − Σ architecture, but work in a transient mode is more adapted. However this converter’s drawback is the large time required to digitize a sample. This thesis aims at studying a new ADC architecture based on an incremental converter, keeping the high precision characteristics and offering a faster conversion. The cascading of an incremental converter with a cyclic converter is presented. The converter is used in incremental mode and produces a residual quantization error. This voltage is then passed to a faster cyclic converter. The conversion still benefit the high precision of incremental conversion while required conversion time is reduced. Another advantage of this new architecture is that both converters share the same hardware, which leads to a very compact converter. The introduced general architecture is flexible: the resolution solved by each conversion is not fixed, thus it is capable to optimize the tradeoff between conversion accuracy and conversion time. Another presented architecture for reducing the conversion time is to use a second-order incremental converter cascaded by a cyclic one. A switched-capacitor implementation is proposed. The developed archi tecture is validated through the realization of two integrated circuits in a CMOS 0.18 μm technology. A circuit with first order only and another with first and second order. A 16-bit ADC with a sampling frequency of 500 Hz is realized. The maximum signal-to-noise ration is 84.8 dB, which is equivalent to 13.8 effective number of bits. The power consumption is 150 μW under 1.65 V and the active area is 0.1 mm2. Compared to other solutions, the results are relatively efficient and competitive in the field of high resolution, with the benefit of a small circuit.