000020403 001__ 20403
000020403 005__ 20130225122140.0
000020403 0247_ $$2urn$$aurn:nbn:ch:rero-004-109399
000020403 0248_ $$aoai:doc.rero.ch:20100915110013-AZ$$pthesis$$prero_explore$$pthesis_urn$$zcdu34$$zreport$$zbook$$zjournal$$zpostprint$$zcdu16$$zpreprint$$zcdu1$$zdissertation$$zunine$$zcdu681
000020403 041__ $$aeng
000020403 080__ $$a681
000020403 100__ $$aRossi, Luca
000020403 245__ $$9eng$$aA/D converters architectures based on cascaded incremental and cyclic structures
000020403 300__ $$a180
000020403 502__ $$92009-08-25$$aThèse de doctorat : Université de Neuchâtel, 2009
000020403 506__ $$ffree
000020403 520__ $$9eng$$aCharacteristics of converters are extremely wide from Gigasamples to a few samples per second for bandwidth and resolution variation from a few bits to more than 20 bits. In the field of high resolution, converters architecture are mostly based on oversampling converters. Delta-sigma converter is a common implementation of this architecture. However, in certain applications, this converter is not very-well suited. In instrumentation and measurements, the continuously operation, the large offset and inaccurate gain of the Δ − Σ does not satisfy the specifications. The incremental converter, who is also based on Δ − Σ architecture, but work in a transient mode is more adapted. However this converter’s drawback is the large time required to digitize a sample. This thesis aims at studying a new ADC architecture based on an incremental converter, keeping the high precision characteristics and offering a faster conversion. The cascading of an incremental converter with a cyclic converter is presented. The converter is used in incremental mode and produces a residual quantization error. This voltage is then passed to a faster cyclic converter. The conversion still benefit the high precision of incremental conversion while required conversion time is reduced. Another advantage of this new architecture is that both converters share the same hardware, which leads to a very compact converter. The introduced general architecture is flexible: the resolution solved by each conversion is not fixed, thus it is capable to optimize the tradeoff between conversion accuracy and conversion time. Another presented architecture for reducing the conversion time is to use a second-order incremental converter cascaded by a cyclic one. A switched-capacitor implementation is proposed. The developed archi tecture is validated through the realization of two integrated circuits in a CMOS 0.18 μm technology. A circuit with first order only and another with first and second order. A 16-bit ADC with a sampling frequency of 500 Hz is realized. The maximum signal-to-noise ration is 84.8 dB, which is equivalent to 13.8 effective number of bits. The power consumption is 150 μW under 1.65 V and the active area is 0.1 mm2. Compared to other solutions, the results are relatively efficient and competitive in the field of high resolution, with the benefit of a small circuit.
000020403 695__ $$9eng$$aAnalog-digital conversion (ADC) ; incremental ; cyclic ; switched-capacitor circuit (SC) ; integrated circuit ; CMOS
000020403 700__ $$aFarine, Pierre-André$$eDir.
000020403 700__ $$aTanner, Steve$$eCodir.
000020403 700__ $$aNys, Olivier$$eCodir.
000020403 700__ $$aWillemin, Michel$$eCodir.
000020403 8564_ $$f00002160.pdf$$qapplication/pdf$$s13747805$$uhttp://doc.rero.ch/record/20403/files/00002160.pdf$$yorder:1$$zTexte intégral
000020403 918__ $$aFaculté des sciences$$bRue Emile-Argand 11, 2007 Neuchâtel$$cInstitut de microtechnique
000020403 919__ $$aUniversité de Neuchâtel$$bNeuchâtel$$ddoc.support@rero.ch
000020403 980__ $$aTHESIS$$bUNINE$$fTH_PHD
000020403 990__ $$a20100915110013-AZ